From: Mikko Rasa Date: Wed, 3 Jul 2013 15:53:32 +0000 (+0300) Subject: Somre more common facilities X-Git-Url: http://git.tdb.fi/?a=commitdiff_plain;h=3c070b8fc92fe0506e29d0c0491038be241f7107;p=model-railway-devices.git Somre more common facilities --- diff --git a/common/adc.c b/common/adc.c new file mode 100644 index 0000000..7c71c3d --- /dev/null +++ b/common/adc.c @@ -0,0 +1,18 @@ +#include "adc.h" + +#define BIT(n) (1<<(n)) + +void adc_init() +{ + // TODO Adjust ADPS bits according to F_CPU + ADMUX = BIT(REFS0); + ADCSRA = BIT(ADEN) | BIT(ADIE) | BIT(ADPS2) | BIT(ADPS1) | BIT(ADPS0); + ADCSRB = 0; + DIDR0 = 0x3F; +} + +void adc_read_async(uint8_t chan) +{ + ADMUX = (ADMUX&0xF0) | (chan&0x0F); + ADCSRA |= BIT(ADSC); +} diff --git a/common/adc.h b/common/adc.h new file mode 100644 index 0000000..d9cff6b --- /dev/null +++ b/common/adc.h @@ -0,0 +1,17 @@ +#ifndef ADC_H_ +#define ADC_H_ + +#include + +#define ADC_SET_CALLBACK(f) \ + ISR(ADC_vect) \ + { \ + uint16_t v = ADCL; \ + v |= ADCH<<8; \ + f(v); \ + } + +void adc_init(); +void adc_read_async(uint8_t); + +#endif diff --git a/common/timer.c b/common/timer.c index 99625f8..491e470 100644 --- a/common/timer.c +++ b/common/timer.c @@ -10,9 +10,7 @@ static void timer_start(uint8_t num, uint32_t period) if(num==0) { if(period<0x100) - { cs = BIT(CS00); - } else if(period<0x800) { cs = BIT(CS01); @@ -40,12 +38,10 @@ static void timer_start(uint8_t num, uint32_t period) OCR0A = period; TIMSK0 = BIT(OCIE0A); } - if(num==1) + else if(num==1) { if(period<0x10000) - { cs = BIT(CS10); - } else if(period<0x80000) { cs = BIT(CS11); @@ -74,6 +70,47 @@ static void timer_start(uint8_t num, uint32_t period) OCR1AL = period; TIMSK1 = BIT(OCIE1A); } + else if(num==2) + { + if(period<0x100) + cs = BIT(CS20); + else if(period<0x800) + { + cs = BIT(CS21); + period /= 8; + } + else if(period<0x2000) + { + cs = BIT(CS21) | BIT(CS20); + period /= 32; + } + else if(period<0x4000) + { + cs = BIT(CS22); + period /= 64; + } + else if(period<0x8000) + { + cs = BIT(CS22) | BIT(CS20); + period /= 128; + } + else if(period<0x10000) + { + cs = BIT(CS22) | BIT(CS21); + period /= 256; + } + else + { + cs = BIT(CS22) | BIT(CS21) | BIT(CS20); + period /= 1024; + if(period>0xFF) + period = 0xFF; + } + TCCR2A = BIT(WGM21); + TCCR2B = cs; + OCR2A = period; + TIMSK2 = BIT(OCIE2A); + } } void timer_start_hz(uint8_t num, uint32_t freq_p, uint8_t freq_q) @@ -98,4 +135,9 @@ void timer_stop(uint8_t num) TCCR1B = 0; TIMSK1 = 0; } + else if(num==2) + { + TCCR2B = 0; + TIMSK2 = 0; + } }